//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/******************************************************************************
**
**  COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       xllp_uart.h
**
**  PURPOSE:        Definitions for Bulverde UART
**
**
******************************************************************************/

#ifndef xllp_uart_h
#define xllp_uart_h

/*
************************************************************************************
*                             CONSTANTS 
************************************************************************************
*/

typedef enum
{
    XLLP_FFUART = 0,
    XLLP_BTUART = 1,
    XLLP_STUART = 2
} XLLP_UARTSelection_T;

/*
************************************************************************************
*                            DATA TYPES 
************************************************************************************
*/

// UART registers
// This type is used by FFUART, BTUART and STUART

typedef struct
{
    XLLP_VUINT32_T RBR_THR_DLL;   // Receive Buffer Reg. (RBR), Transmit Holding Reg. (THR) and DLL
    XLLP_VUINT32_T IER_DLH;       // Interrupt Enable Reg. (IER) and Baud Divisor Higher Byte Reg. (DLH)
    XLLP_VUINT32_T IIR_FCR;       // Interrupt ID Reg. (read only) and FIFO Control Reg. (write only)
    XLLP_VUINT32_T LCR;           // Line Control Reg.
    XLLP_VUINT32_T MCR;           // Modem Control Reg.
    XLLP_VUINT32_T LSR;           // Line Status Reg.
    XLLP_VUINT32_T MSR;           // Modem Status Reg.
    XLLP_VUINT32_T SPR;           // Scratch Pad Reg.
    XLLP_VUINT32_T ISR;           // Slow Infrared Select Reg.
    XLLP_VUINT32_T FOR;           // FIFO Occupancy Reg.
    XLLP_VUINT32_T ABR;           // Autobaud Control Reg.
    XLLP_VUINT32_T ACR;           // Autobaud Count Reg.
} XLLP_UART_T, *P_XLLP_UART_T;

typedef struct
{
    XLLP_UARTSelection_T UARTSelection; // Configure an FF or BT or STUART ?

    P_XLLP_UART_T   pUARTRegs;      // Pointer to the UART registers
    P_XLLP_GPIO_T   pGPIORegs;      // Pointer to the GPIO registers
    P_XLLP_BCR_T    pBCRRegs;       // Pointer to the GPIO registers
    P_XLLP_CLKMGR_T pCLKMGRRegs;    // Pointer to the Clock Manager registers

    // user specified values to write to the UART registers.
    XLLP_VUINT32_T  DLL_Value;      // Value to write to DLL
    XLLP_VUINT32_T  DLH_Value;      // Value to write to DLH
    XLLP_VUINT32_T  LCR_Value;      // Value to write to LCR
    XLLP_VUINT32_T  FCR_Value;      // Value to write to FCR
    XLLP_VUINT32_T  IER_Value;      // Value to write to IER
    XLLP_VUINT32_T  ABR_Value;      // Value to write to ABR
    XLLP_VUINT32_T  MCR_Value;      // Value to write to MCR
    XLLP_VUINT32_T  ISR_Value;      // Value to write to ISR

    XLLP_VUINT32_T  BCR_MISCWR1_Value; // Value to write to BCR Miscellaneous Write Register 1

} XLLP_UART_HANDLE_T, *P_XLLP_UART_HANDLE_T;

// Masks for IER Reg.
// Note:
//      - user needs to program the GPIO reg. before enabling the unit
//      - NRZ is used in UART mode only, not for infrared mode
//      - user needs to make sure that DMA and TIE and RAVIE are not set to 1 at the same time
#define XLLP_IER_RAVIE     XLLP_BIT_0
#define XLLP_IER_TIE       XLLP_BIT_1
#define XLLP_IER_RLSE      XLLP_BIT_2
#define XLLP_IER_MIE       XLLP_BIT_3
#define XLLP_IER_RTOIE     XLLP_BIT_4
#define XLLP_IER_NRZE      XLLP_BIT_5
#define XLLP_IER_UUE       XLLP_BIT_6
#define XLLP_IER_DMAE      XLLP_BIT_7

// Masks for Interrupt Identification Reg. (IIR)
// Note: IIR (read only) is located at the same address as the FCR (write only)
#define XLLP_IIR_IP        XLLP_BIT_0
#define XLLP_IIR_RLS       (XLLP_BIT_1 + XLLP_BIT_2)
#define XLLP_IIR_RDA       XLLP_BIT_2
#define XLLP_IIR_TOD       (XLLP_BIT_2 + XLLP_BIT_3)
#define XLLP_IIR_TFIFO     XLLP_BIT_1
#define XLLP_IIR_ABL       XLLP_BIT_4
#define XLLP_IIR_EOC       XLLP_BIT_5
#define XLLP_IIR_FIFOES    (XLLP_BIT_6 + XLLP_BIT_7)

// Masks for Auto-Baud Control Reg. (ABR)
// Note: IIR (read only) is located at the same address as the FCR (write only)
#define XLLP_ABR_ABE       XLLP_BIT_0
#define XLLP_ABR_ABLIE     XLLP_BIT_1
#define XLLP_ABR_ABUP      XLLP_BIT_2
#define XLLP_ABR_ABT       XLLP_BIT_3

// Masks for FIFO Control Register
#define XLLP_FCR_TRFIFOE   XLLP_BIT_0
#define XLLP_FCR_RESETRF   XLLP_BIT_1
#define XLLP_FCR_RESETTF   XLLP_BIT_2
#define XLLP_FCR_TIL       XLLP_BIT_3
#define XLLP_FCR_TRAIL     XLLP_BIT_4
#define XLLP_FCR_BUS       XLLP_BIT_5
#define XLLP_FCR_ITL1      0
#define XLLP_FCR_ITL8      XLLP_BIT_6
#define XLLP_FCR_ITL16     XLLP_BIT_7
#define XLLP_FCR_ITL32     (XLLP_BIT_6 + XLLP_BIT_7)

// Masks for FIFO Occupancy Register
#define XLLP_FOR_BYTECOUNT (XLLP_BIT_0 + XLLP_BIT_1 + XLLP_BIT_2 + XLLP_BIT_3 + XLLP_BIT_4 + XLLP_BIT_5)

// Masks for Line Control Reg. (LCR)
#define XLLP_LCR_WLS5      0
#define XLLP_LCR_WLS6      XLLP_BIT_0
#define XLLP_LCR_WLS7      XLLP_BIT_1
#define XLLP_LCR_WLS8      (XLLP_BIT_0 + XLLP_BIT_1)
#define XLLP_LCR_STB       XLLP_BIT_2
#define XLLP_LCR_PEN       XLLP_BIT_3
#define XLLP_LCR_EPS       XLLP_BIT_4
#define XLLP_LCR_STKYP     XLLP_BIT_5
#define XLLP_LCR_SB        XLLP_BIT_6
#define XLLP_LCR_DLAB      XLLP_BIT_7

// Masks for Line Status Reg. (LSR)
#define XLLP_LSR_DR        XLLP_BIT_0
#define XLLP_LSR_OE        XLLP_BIT_1
#define XLLP_LSR_PE        XLLP_BIT_2
#define XLLP_LSR_FE        XLLP_BIT_3
#define XLLP_LSR_BI        XLLP_BIT_4
#define XLLP_LSR_TDRQ      XLLP_BIT_5
#define XLLP_LSR_TEMT      XLLP_BIT_6
#define XLLP_LSR_FIFOE     XLLP_BIT_7

// Masks for Modem Control Reg.
#define XLLP_MCR_DTR       XLLP_BIT_0
#define XLLP_MCR_RTS       XLLP_BIT_1
#define XLLP_MCR_OUT1      XLLP_BIT_2
#define XLLP_MCR_OUT2      XLLP_BIT_3
#define XLLP_MCR_LOOP      XLLP_BIT_4
#define XLLP_MCR_AFE       XLLP_BIT_5

// Masks for Modem Status Reg. (MSR)
#define XLLP_MSR_DCTS      XLLP_BIT_0
#define XLLP_MSR_DDSR      XLLP_BIT_1
#define XLLP_MSR_TERI      XLLP_BIT_2
#define XLLP_MSR_DDCD      XLLP_BIT_3
#define XLLP_MSR_CTS       XLLP_BIT_4
#define XLLP_MSR_DSR       XLLP_BIT_5
#define XLLP_MSR_RI        XLLP_BIT_6
#define XLLP_MSR_DCD       XLLP_BIT_7

// Masks for Infrared Selection Reg. (ISR)
#define XLLP_ISR_XMITIR    XLLP_BIT_0
#define XLLP_ISR_RCVEIR    XLLP_BIT_1
#define XLLP_ISR_XMODE     XLLP_BIT_2
#define XLLP_ISR_TXPL      XLLP_BIT_3
#define XLLP_ISR_RXPL      XLLP_BIT_4

// Minimum values of divisors programmed in divisor latch reg.
#define XLLP_FFDIVISOR_MIN 4    // FFUART divisor
#define XLLP_BTDIVISOR_MIN 1    // BTUART divisor
#define XLLP_STDIVISOR_MIN 4    // STUART divisor

#define XLLP_THR_VALIDBITS 0xFF
#define XLLP_RBR_VALIDBITS 0xFF
#define XLLP_DLL_VALIDBITS 0xFF
#define XLLP_DLH_VALIDBITS 0xFF
#define XLLP_SPR_VALIDBITS 0xFF

#define XLLP_RETRY   10

#define XLLP_NUM_BUF_DEFAULT    2
#define XLLP_BUFF_SIZE_DEFAULT  64
#define XLLP_XFER_LEN_DEFAULT   128

#define XLLP_DLL_4800BAUD   0xC0
#define XLLP_DLH_4800BAUD   0x00

#define XLLP_DLL_9600BAUD   0x60
#define XLLP_DLH_9600BAUD   0x00

#define XLLP_DLL_19200BAUD  0x30
#define XLLP_DLH_19200BAUD  0x00

#define XLLP_DLL_38400BAUD  0x18
#define XLLP_DLH_38400BAUD  0x00

#define XLLP_DLL_57600BAUD  0x10
#define XLLP_DLH_57600BAUD  0x00

#define XLLP_DLL_115200BAUD 0x08
#define XLLP_DLH_115200BAUD 0x00

void XllpUartInit(P_XLLP_UART_HANDLE_T pUARTHandle);

#endif /* xllp_uart_h */
